At the IEEE International Electronic Devices Conference (IEDM) held in San Francisco, TSMC, a global wafer foundry giant, announced more details about its highly anticipated 2-nanometer (N2) process technology. It is reported that compared to the previous generation process, the N2 process has improved performance by 15%, reduced power consumption by up to 30%, and significantly improved energy efficiency. In addition, thanks to the application of surround gate (GAA) nanosheet transistors and N2 NanoFlex technology, the transistor density has also increased by 1.15 times.